The MPEG-2 Video Decoder Chipset includes an FPGA and a FLASH preconfigured with SOC's MPEG-2 Decoder IP Core. It is an ASIC that receives MPEG-2 compressed stream and outputs decompressed video and audio data.
|DC-VA-MPEG2-8b-30-1080-C||Video+Audio||8 bits per pixel||up to 30fps|
|DC-V-MPEG2-8b-30-1080-C||Video Only||8 bits per pixel||up to 30fps|
|DC-VA-MPEG2-10b-30-1080-C||Video+Audio||Up to 10 bits per pixel||up to 30fps|
|DC-V-MPEG2-10b-30-1080-C||Video Only||Up to 10 bits per pixel||up to 30fps|
|DC-VA-MPEG2-8b-60-1080-C||Video+Audio||8 bits per pixel||up to 60fps|
|DC-V-MPEG2-8b-60-1080-C||Video Only||8 bits per pixel||up to 60fps|
|DC-VA-MPEG2-10b-60-1080-C||Video+Audio||Up to 10 bits per pixel||up to 60fps|
|DC-V-MPEG2-10b-60-1080-C||Video Only||Up to 10 bits per pixel||up to 60fps|
SOC offers compatible high-performance peripheral IP cores for common functions.
The MPEG-2 Video Decoder Chipset can be evaluated on SOC'sDevelopment Boards.The boards can also be used for product development, having the ports and extensions necessary for most video-based applications. SOC provides and licenses reference designs and board files if needed.
Begin the evaluation process by any of these methods: