SOC offers high-performance H.264 IP Cores, H.265 IP Cores, and MPEG-2 IP Cores for encoding, decoding, and transcoding video and audio data. SOC's MPEG CODEC engines offer unbeatable performance in areas of low-latency, power-efficiency, and silicon footprint with no sacrifices in quality. The ip core format offers the greatest degree of flexibility for hardware engineers. Their small footprint allows cores to be added to existing FPGA systems alongside existing IP, creating very tightly-coupled multimedia streaming solutions.
SOC has managed to fit an incredible amount of processing power into a tiny resource footprint.
SOC IP Cores are designed to work on mid-level Intel and Xilinx FPGAS or SoCs.
SOC's customers span a wide range of industries from broadcast to video surveillance. Many have very strict bandwidth and video quality standards. SOC has developed a series of standards-compliant CODEC IP Cores that produce sharp quality at very low latency, and using very few resources.
SOC's all-hardware architecture executes in parallel as much as possible. Executing many stages per clock cycle enables real-time capture-to-display solutions. SOC's 0.25ms latency is among the lowest in the industry, and is superior to CPU and DSP-based solutions.
SOC's MPEG2, H.264, and H.265 encoders, decoders, and transcoders use proprietary micro-parallel all-hardware processing. Power savings can mean longer battery life for wireless applications like solar-powered/remote surveillance, portable high-definition (HD) cinematography, and FPV vehicle control; or huge cost savings for bulk video-processing operations.
Full CODECs can fit into standard off-the-shelf XILINX and Intel FPGAs, usually with plenty of resources available for additional customer IP.