H.264 4K Video Decoder IP Core
(H.264 4K Video/Audio Decoder IP Core)


 The H.264 4K Video Decoder IP Core is a real-time video decoder that supports H.264 video or video/audio streams of up to 4K/60 (4K-p/60) (4096×2160 at 60fps) resolution.

Deliverables


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide

Specifications


Standard:H.264/AVC (ISO/IEC14496-10)
Profile:High Profile
Level:5.2
Max Resolution:Up to 4K(4096 × 2160p) at 60fps
Chroma:4:2:0 or 4:2:2
Precision:8 or 10 bit
Input:Elementary or Transport Stream
Latency:0.5ms
FPGA Resources:
Xilinx:
LUTs:60,000
Block RAM:40Kb
DSPs:25
Intel:
ALMs:40,000
Block RAM:36Kb
DSPs:25
Note:Resource values are for 30fps. Double the resource values for 60fps.

Product Evaluation Kits


 The H.264 4K Video Decoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:



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