CODEC FPGA IP Cores

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H.264 8K Video Decoder IP Core
(H.264 8K Video/Audio Decoder IP Core)

SOC provides an H.264/AVC Decoder IP Core for up to 8K (7680 × 4320) resolution.

Specifications

Standard

H.264/AVC (ISO/IEC14496-10)

Profile

Up to High Profile

Levels

5.2

Max Resolution

8K (7680 × 4320p) at 60fps

Chroma

4:2:2
4:2:0

Precision

8-bits
10-bit

Input Formats

Elementary Stream (ES)
Transport Stream (TS)

Latency

~1 ms

FPGA Resources

Xilinx

LUTs	170,000
Block RAM	14Mb
DSPs	100
Example FPGA	Zynq-7000 Kintex-7000

Intel

ALMs	120,000
Block RAM	12Mb
DSPs	100
Example FPGAs	Stratix-V Arria-10

Note

Resource values are for 30fps. Double the resource values for 60fps.

Product Table

Code	Video/Audio	Precision	Framerate
DC-VA-H264-8b-30-8K-IP	Video+Audio	8 bits per pixel	up to 30fps
DC-V-H264-8b-30-8K-IP	Video Only	8 bits per pixel	up to 30fps
DC-VA-H264-10b-30-8K-IP	Video+Audio	Up to 10 bits per pixel	up to 30fps
DC-V-H264-10b-30-8K-IP	Video Only	Up to 10 bits per pixel	up to 30fps
DC-VA-H264-8b-60-8K-IP	Video+Audio	8 bits per pixel	up to 60fps
DC-V-H264-8b-60-8K-IP	Video Only	8 bits per pixel	up to 60fps
DC-VA-H264-10b-60-8K-IP	Video+Audio	Up to 10 bits per pixel	up to 60fps
DC-V-H264-10b-60-8K-IP	Video Only	Up to 10 bits per pixel	up to 60fps

Deliverables

IP Core as an FPGA-targeted Netlist
Core instantiation reference design
Integration Guide, API Register Guide

Product Evaluation Kits

The H.264 8K Video Decoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process by any of these methods:

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