H.264 HD Video Decoder IP Core
(H.264 HD Video/Audio Decoder IP Core)


  The H.264/AVC HD Video Decoder IP Core is a high-performance, fault-tolerant real-time decoder of HD video or video/audio data. It can handle resolutions up to 1920x1080 and framerates up to 120fps. The core detects incoming video parameters and adapts accordingly. It is ideal for applications that require hardware-grade reliability and fault-tolerant operation.

Deliverables


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide

Specifications


Standard:H.264/AVC (ISO/IEC14496-10)
Profile:High Profile
Level:5.2
Max Resolution:Up to FHD(2048 × 1080p) at 60fps
Chroma:4:2:0 or 4:2:2
Precision:8 or 10 bit
Input:Elementary or Transport Stream
Latency:0.25ms
FPGA Resources:
Xilinx:
LUTs:60,000
Block RAM:36Kb
DSPs:25
Intel:
ALMs:40,000
Block RAM:36Kb
DSPs:25

Product Evaluation Kits


 The H.264 HD Video Decoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:



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