The H.264 to MPEG-2 Transcoder IP Core is a stream converter engineered based on SOC's ultra-low latency H.264 Video Decoder and the MPEG-2 Video Encoder cores. The H.264 to MPEG-2 Transcoder IP Core provides low-latency, and high quality video conversion from H.264 streams of any profile to MPEG-2 streams of any profile.
The H.264 to MPEG-2 Transcoder IP Core can fit into a Xilinx Artix-7 A200T FPGA for one channel transcoding, and larger FPGAs for multi-channel transcoding.
| Standard: | MPEG2(ISO/IEC 13818) and H.264(ISO/IEC14496-10) |
|---|---|
| Profiles: | High, Main or Baseline |
| Resolution: | Up to FHD(2048 × 1080p) at 60 fps |
| Chroma: | 4:2:0 or 4:2:2 |
| Input: | Elementary or Transport Stream |
| Output: | Elementary or Transport Stream |
| Latency: | 0.5 ms |
The H.264 to MPEG-2 Transcoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.
Begin the evaluation process through any of these methods: