H.265 HD Video Encoder IP Core
(H.265 HD Video/Audio Encoder IP Core)


  The H.265 HD Video Encoder IP Core is a new high-performance engine from SOC. It uses SOC's all-hardware architecture and efficient design methodology to offer superior performance.

Deliverables


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide

Specifications


Standard:H.265/HEVC (ISO/IEC 23008-2 MPEG-H Part 2)
Resolution/FPS:Up to FHD(2048 × 1080p) at 60 fps
Frame Types:I, P
Chroma:4:2:0
Precision:8 bit
Output:Elementary or Transport Stream
Latency:0.25 ms
Bitrate:
  • Variable Bitrate, Constant Bitrate or Constant-QP
  • 3 - 200Mbps, 10Mbps Average for 1080p60
Entropy Coding:CAVLC or CABAC
FPGA Resources:
Xilinx:
LUTs:180,000
Block RAM:10Mb
DSPs:450
Intel:
ALMs:120,000
Block RAM:7Mb
DSPs:450

Product Evaluation Kits


 The H.265 HD Video Encoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:



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