MPEG-2 Video Encoder IP Core
(MPEG-2 Video/Audio Encoder IP Core)


  The MPEG-2 Video Encoder IP Core is a high-performance encoder of single or multiple MPEG-2 video streams. It is implemented using proprietary single-clock driven, all-hardware parallel architecture without a microprocessor.

Deliverables


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide

Specifications


Standard:MPEG-2/H.262 (ISO/IEC 13818)
Resolution/FPS:Up to FHD(2048 × 1080p) at 60 fps
Frame Types:I, P or B
Chroma:4:2:0 or 4:2:2
Precision:8 bit
Output:Elementary or Transport Stream
Latency:0.25 ms
Bitrate:
  • Variable Bitrate, Constant Bitrate or Constant-QP
  • 10 - 400Mbps, 20Mbps Average for 1080p60
FPGA Resources:
Xilinx:
LUTs:50,000
Block RAM:1.6Mb
DSPs:200
Intel:
ALMs:30,000
Block RAM:15Mb
DSPs:210

Product Evaluation Kits


 The MPEG-2 Video Encoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:



Request Information
© System-On-Chip Technologies 2022