MPEG-2 to H.264 Transcoder IP Core


  The MPEG-2 to H264 Transcoder IP Core is based on SOC's low-latency MPEG-2 Decoder and H.264 Encoder IP Cores. The transcoder provides low-latency and high quality video conversion from MPEG-2 streams of all profiles to H.264 of all profiles.

The MPEG-2 to H264 Transcoder IP core can fit into a Xilinx Artix-7 A200T FPGA for single-channel transcoding, or larger FPGAs for multi-channel transcoding.

Deliverables


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide

Specifications


Standard:MPEG2(ISO/IEC 13818) and H.264(ISO/IEC14496-10)
Profiles:High, Main or Baseline
Resolution:Up to FHD(2048 × 1080p) at 60 fps
Chroma:4:2:0 or 4:2:2
Input:Elementary or Transport Stream
Output:Elementary or Transport Stream
Latency:0.5 ms

Product Evaluation Kits


 The MPEG-2 to H.264 Transcoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:



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