H.264 4K Video Encoder IP Core
(H.264 4K Video/Audio Encoder IP Core)

  SOC provides an H.264 4K encoder IP Core for Xilinx and Intel FPGAs. The encoder supports up to 4K/60 (4096 × 2160 @60fps) resolution. Parameters are configurable at run-time through API registers.

Slim Versions

  There are two slimmed-down versions available. The I+P-Frame Slim version uses 50% of standard logic resources, I-Frame-Only Slim version uses only 30% of the standard logic resources. Slim versions are suitable for resource-constrained, low-density FPGAS, if higher bitrates are acceptable.


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide


Standard:H.264/AVC (ISO/IEC14496-10)
Resolution/FPS:Up to 4K(4096 × 2160p) at 60fps
Frame Types:I, P or B
Chroma:4:2:0 or 4:2:2
Precision:8 or 10 bit
Output:Elementary or Transport Stream
  • Variable Bitrate, Constant Bitrate or Constant-QP
  • 12 - 200Mbps, 25Mbps Average for 2160p60
Entropy Coding:CAVLC or CABAC
FPGA Resources:
Block RAM:10Mb
Block RAM:6Mb
Note:Resource values are for 30fps. Double the resource values for 60fps.

Product Evaluation Kits

 The H.264 4K Video Encoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:

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