MPEG-2 Video Decoder IP Core
(MPEG-2 Video/Audio Decoder IP Core)


  The MPEG-2 Video Decoder IP Core is a versatile, high-performance video decoding engine that supports all standard resolutions and frame rates. It is trusted by broadcast customers as it supports all required features to deliver video to living rooms.

Deliverables


  1. IP Core as an FPGA-targeted Netlist
  2. Core instantiation reference design
  3. Integration Guide, API Register Guide

Specifications


Standard:MPEG-2/H.262 (ISO/IEC 13818)
Profile:Simple, Main, High or 422
Level:High
Max Resolution:Up to FHD(2048 × 1080p) at 60fps
Chroma:4:2:0 or 4:2:2
Precision:8 or 10 bit
Input:Elementary or Transport Stream
Latency:0.25ms
FPGA Resources:
Xilinx:
LUTs:12,000
Block RAM:756Kb
DSPs:54
Intel:
ALMs:40,000
Block RAM:36Kb
DSPs:54

Product Evaluation Kits


 The MPEG-2 Video Decoder IP Core can be evaluated on SOC's Evaluation Kits. Evaluation kits include a carrier-board with all the ports and extensions needed for most video-based applications. The module and carrier board firmware are reconfigurable, and we can license board files if needed.

Begin the evaluation process through any of these methods:



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